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https://github.com/luau-lang/luau.git
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8453570658
* `Luau.Analyze.CLI` now has experimental support for concurrent type checking. Use the option `-jN` where `N` is the number of threads to spawn. * Improve typechecking performance by ~17% by making the function `Luau::follow` much more efficient. * Tighten up the type of `os.date` * Removed `ParseOptions::allowTypeAnnotations` and `ParseOptions::supportContinueStatement` New solver * Improve the reliability of function overload resolution * More work toward supporting parallel type checking * Fix a bug in inference of `==` and `~=` which would erroneously infer that the operands were `boolean` * Better error reporting when `for...in` loops are used incorrectly. CodeGen * Fix unwind registration when libunwind is used on Linux * Fixed replaced IR instruction use count * Convert X64 unwind info generation to standard prologue * Implement A64 unwind info support for Dwarf2 * Live in/out data for linear blocks is now created * Add side-exit VM register requirements to the IR dump * Reuse ConstPropState between block chains * Remove redundant base update --------- Co-authored-by: Arseny Kapoulkine <arseny.kapoulkine@gmail.com> Co-authored-by: Vyacheslav Egorov <vegorov@roblox.com>
128 lines
4.3 KiB
C++
128 lines
4.3 KiB
C++
// This file is part of the Luau programming language and is licensed under MIT License; see LICENSE.txt for details
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#include "EmitBuiltinsX64.h"
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#include "Luau/AssemblyBuilderX64.h"
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#include "Luau/Bytecode.h"
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#include "Luau/IrCallWrapperX64.h"
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#include "Luau/IrRegAllocX64.h"
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#include "EmitCommonX64.h"
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#include "NativeState.h"
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#include "lstate.h"
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namespace Luau
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{
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namespace CodeGen
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{
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namespace X64
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{
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static void emitBuiltinMathFrexp(IrRegAllocX64& regs, AssemblyBuilderX64& build, int ra, int arg, int nresults)
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{
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IrCallWrapperX64 callWrap(regs, build);
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callWrap.addArgument(SizeX64::xmmword, luauRegValue(arg));
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callWrap.addArgument(SizeX64::qword, sTemporarySlot);
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callWrap.call(qword[rNativeContext + offsetof(NativeContext, libm_frexp)]);
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build.vmovsd(luauRegValue(ra), xmm0);
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if (nresults > 1)
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{
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build.vcvtsi2sd(xmm0, xmm0, dword[sTemporarySlot + 0]);
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build.vmovsd(luauRegValue(ra + 1), xmm0);
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}
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}
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static void emitBuiltinMathModf(IrRegAllocX64& regs, AssemblyBuilderX64& build, int ra, int arg, int nresults)
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{
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IrCallWrapperX64 callWrap(regs, build);
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callWrap.addArgument(SizeX64::xmmword, luauRegValue(arg));
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callWrap.addArgument(SizeX64::qword, sTemporarySlot);
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callWrap.call(qword[rNativeContext + offsetof(NativeContext, libm_modf)]);
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build.vmovsd(xmm1, qword[sTemporarySlot + 0]);
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build.vmovsd(luauRegValue(ra), xmm1);
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if (nresults > 1)
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build.vmovsd(luauRegValue(ra + 1), xmm0);
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}
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static void emitBuiltinMathSign(IrRegAllocX64& regs, AssemblyBuilderX64& build, int ra, int arg)
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{
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ScopedRegX64 tmp0{regs, SizeX64::xmmword};
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ScopedRegX64 tmp1{regs, SizeX64::xmmword};
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ScopedRegX64 tmp2{regs, SizeX64::xmmword};
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ScopedRegX64 tmp3{regs, SizeX64::xmmword};
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build.vmovsd(tmp0.reg, luauRegValue(arg));
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build.vxorpd(tmp1.reg, tmp1.reg, tmp1.reg);
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// Set tmp2 to -1 if arg < 0, else 0
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build.vcmpltsd(tmp2.reg, tmp0.reg, tmp1.reg);
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build.vmovsd(tmp3.reg, build.f64(-1));
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build.vandpd(tmp2.reg, tmp2.reg, tmp3.reg);
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// Set mask bit to 1 if 0 < arg, else 0
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build.vcmpltsd(tmp0.reg, tmp1.reg, tmp0.reg);
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// Result = (mask-bit == 1) ? 1.0 : tmp2
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// If arg < 0 then tmp2 is -1 and mask-bit is 0, result is -1
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// If arg == 0 then tmp2 is 0 and mask-bit is 0, result is 0
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// If arg > 0 then tmp2 is 0 and mask-bit is 1, result is 1
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build.vblendvpd(tmp0.reg, tmp2.reg, build.f64x2(1, 1), tmp0.reg);
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build.vmovsd(luauRegValue(ra), tmp0.reg);
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}
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static void emitBuiltinType(IrRegAllocX64& regs, AssemblyBuilderX64& build, int ra, int arg)
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{
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ScopedRegX64 tmp0{regs, SizeX64::qword};
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ScopedRegX64 tag{regs, SizeX64::dword};
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build.mov(tag.reg, luauRegTag(arg));
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build.mov(tmp0.reg, qword[rState + offsetof(lua_State, global)]);
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build.mov(tmp0.reg, qword[tmp0.reg + qwordReg(tag.reg) * sizeof(TString*) + offsetof(global_State, ttname)]);
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build.mov(luauRegValue(ra), tmp0.reg);
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}
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static void emitBuiltinTypeof(IrRegAllocX64& regs, AssemblyBuilderX64& build, int ra, int arg)
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{
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IrCallWrapperX64 callWrap(regs, build);
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callWrap.addArgument(SizeX64::qword, rState);
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callWrap.addArgument(SizeX64::qword, luauRegAddress(arg));
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callWrap.call(qword[rNativeContext + offsetof(NativeContext, luaT_objtypenamestr)]);
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build.mov(luauRegValue(ra), rax);
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}
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void emitBuiltin(IrRegAllocX64& regs, AssemblyBuilderX64& build, int bfid, int ra, int arg, OperandX64 arg2, int nparams, int nresults)
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{
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switch (bfid)
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{
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case LBF_MATH_FREXP:
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LUAU_ASSERT(nparams == 1 && (nresults == 1 || nresults == 2));
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return emitBuiltinMathFrexp(regs, build, ra, arg, nresults);
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case LBF_MATH_MODF:
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LUAU_ASSERT(nparams == 1 && (nresults == 1 || nresults == 2));
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return emitBuiltinMathModf(regs, build, ra, arg, nresults);
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case LBF_MATH_SIGN:
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LUAU_ASSERT(nparams == 1 && nresults == 1);
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return emitBuiltinMathSign(regs, build, ra, arg);
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case LBF_TYPE:
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LUAU_ASSERT(nparams == 1 && nresults == 1);
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return emitBuiltinType(regs, build, ra, arg);
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case LBF_TYPEOF:
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LUAU_ASSERT(nparams == 1 && nresults == 1);
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return emitBuiltinTypeof(regs, build, ra, arg);
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default:
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LUAU_ASSERT(!"Missing x64 lowering");
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break;
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}
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}
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} // namespace X64
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} // namespace CodeGen
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} // namespace Luau
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