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Remove redundant checks from assertions

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This commit is contained in:
Arseny Kapoulkine 2024-02-15 09:17:12 -08:00
parent 8c0115c03a
commit 2393d2b4a6
1 changed files with 5 additions and 5 deletions
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10
CodeGen/src/AssemblyBuilderA64.cpp
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@ -586,7 +586,7 @@ void AssemblyBuilderA64::fadd(RegisterA64 dst, RegisterA64 src1, RegisterA64 src
} }
else if (dst.kind == KindA64::s) else if (dst.kind == KindA64::s)
{ {
LUAU_ASSERT(dst.kind == KindA64::s && src1.kind == KindA64::s && src2.kind == KindA64::s); LUAU_ASSERT(src1.kind == KindA64::s && src2.kind == KindA64::s);
placeR3("fadd", dst, src1, src2, 0b11110'00'1, 0b0010'10); placeR3("fadd", dst, src1, src2, 0b11110'00'1, 0b0010'10);
} }
@ -608,7 +608,7 @@ void AssemblyBuilderA64::fdiv(RegisterA64 dst, RegisterA64 src1, RegisterA64 src
} }
else if (dst.kind == KindA64::s) else if (dst.kind == KindA64::s)
{ {
LUAU_ASSERT(dst.kind == KindA64::s && src1.kind == KindA64::s && src2.kind == KindA64::s); LUAU_ASSERT(src1.kind == KindA64::s && src2.kind == KindA64::s);
placeR3("fdiv", dst, src1, src2, 0b11110'00'1, 0b0001'10); placeR3("fdiv", dst, src1, src2, 0b11110'00'1, 0b0001'10);
} }
@ -630,7 +630,7 @@ void AssemblyBuilderA64::fmul(RegisterA64 dst, RegisterA64 src1, RegisterA64 src
} }
else if (dst.kind == KindA64::s) else if (dst.kind == KindA64::s)
{ {
LUAU_ASSERT(dst.kind == KindA64::s && src1.kind == KindA64::s && src2.kind == KindA64::s); LUAU_ASSERT(src1.kind == KindA64::s && src2.kind == KindA64::s);
placeR3("fmul", dst, src1, src2, 0b11110'00'1, 0b0000'10); placeR3("fmul", dst, src1, src2, 0b11110'00'1, 0b0000'10);
} }
@ -652,7 +652,7 @@ void AssemblyBuilderA64::fneg(RegisterA64 dst, RegisterA64 src)
} }
else if (dst.kind == KindA64::s) else if (dst.kind == KindA64::s)
{ {
LUAU_ASSERT(dst.kind == KindA64::s && src.kind == KindA64::s); LUAU_ASSERT(src.kind == KindA64::s);
placeR1("fneg", dst, src, 0b000'11110'00'1'0000'10'10000); placeR1("fneg", dst, src, 0b000'11110'00'1'0000'10'10000);
} }
@ -681,7 +681,7 @@ void AssemblyBuilderA64::fsub(RegisterA64 dst, RegisterA64 src1, RegisterA64 src
} }
else if (dst.kind == KindA64::s) else if (dst.kind == KindA64::s)
{ {
LUAU_ASSERT(dst.kind == KindA64::s && src1.kind == KindA64::s && src2.kind == KindA64::s); LUAU_ASSERT(src1.kind == KindA64::s && src2.kind == KindA64::s);
placeR3("fsub", dst, src1, src2, 0b11110'00'1, 0b0011'10); placeR3("fsub", dst, src1, src2, 0b11110'00'1, 0b0011'10);
} }