2022-05-26 21:33:48 +01:00
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// This file is part of the Luau programming language and is licensed under MIT License; see LICENSE.txt for details
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#pragma once
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#include "Luau/Common.h"
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#include "Luau/Condition.h"
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#include "Luau/Label.h"
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#include "Luau/OperandX64.h"
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#include "Luau/RegisterX64.h"
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#include <string>
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#include <vector>
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namespace Luau
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{
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namespace CodeGen
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{
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2022-10-13 23:59:53 +01:00
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enum class RoundingModeX64
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{
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RoundToNearestEven = 0b00,
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RoundToNegativeInfinity = 0b01,
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RoundToPositiveInfinity = 0b10,
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RoundToZero = 0b11,
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};
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2022-05-26 21:33:48 +01:00
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class AssemblyBuilderX64
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{
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public:
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explicit AssemblyBuilderX64(bool logText);
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~AssemblyBuilderX64();
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// Base two operand instructions with 9 opcode selection
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void add(OperandX64 lhs, OperandX64 rhs);
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void sub(OperandX64 lhs, OperandX64 rhs);
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void cmp(OperandX64 lhs, OperandX64 rhs);
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void and_(OperandX64 lhs, OperandX64 rhs);
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void or_(OperandX64 lhs, OperandX64 rhs);
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void xor_(OperandX64 lhs, OperandX64 rhs);
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// Binary shift instructions with special rhs handling
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void sal(OperandX64 lhs, OperandX64 rhs);
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void sar(OperandX64 lhs, OperandX64 rhs);
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void shl(OperandX64 lhs, OperandX64 rhs);
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void shr(OperandX64 lhs, OperandX64 rhs);
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// Two operand mov instruction has additional specialized encodings
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void mov(OperandX64 lhs, OperandX64 rhs);
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void mov64(RegisterX64 lhs, int64_t imm);
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2022-08-11 21:42:54 +01:00
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void movsx(RegisterX64 lhs, OperandX64 rhs);
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void movzx(RegisterX64 lhs, OperandX64 rhs);
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2022-05-26 21:33:48 +01:00
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// Base one operand instruction with 2 opcode selection
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void div(OperandX64 op);
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void idiv(OperandX64 op);
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void mul(OperandX64 op);
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2022-08-11 21:42:54 +01:00
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void imul(OperandX64 op);
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2022-05-26 21:33:48 +01:00
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void neg(OperandX64 op);
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void not_(OperandX64 op);
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void dec(OperandX64 op);
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void inc(OperandX64 op);
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2022-08-11 21:42:54 +01:00
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// Additional forms of imul
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void imul(OperandX64 lhs, OperandX64 rhs);
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void imul(OperandX64 dst, OperandX64 lhs, int32_t rhs);
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2022-05-26 21:33:48 +01:00
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void test(OperandX64 lhs, OperandX64 rhs);
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void lea(OperandX64 lhs, OperandX64 rhs);
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void push(OperandX64 op);
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void pop(OperandX64 op);
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void ret();
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// Control flow
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void jcc(Condition cond, Label& label);
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void jmp(Label& label);
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void jmp(OperandX64 op);
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2022-07-08 02:05:31 +01:00
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void call(Label& label);
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void call(OperandX64 op);
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2022-07-21 21:36:41 +01:00
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void int3();
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// AVX
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void vaddpd(OperandX64 dst, OperandX64 src1, OperandX64 src2);
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void vaddps(OperandX64 dst, OperandX64 src1, OperandX64 src2);
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void vaddsd(OperandX64 dst, OperandX64 src1, OperandX64 src2);
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void vaddss(OperandX64 dst, OperandX64 src1, OperandX64 src2);
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2022-07-21 21:36:41 +01:00
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void vsubsd(OperandX64 dst, OperandX64 src1, OperandX64 src2);
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void vmulsd(OperandX64 dst, OperandX64 src1, OperandX64 src2);
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void vdivsd(OperandX64 dst, OperandX64 src1, OperandX64 src2);
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void vxorpd(OperandX64 dst, OperandX64 src1, OperandX64 src2);
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2022-08-11 21:42:54 +01:00
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void vucomisd(OperandX64 src1, OperandX64 src2);
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void vcvttsd2si(OperandX64 dst, OperandX64 src);
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void vcvtsi2sd(OperandX64 dst, OperandX64 src1, OperandX64 src2);
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2022-10-13 23:59:53 +01:00
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void vroundsd(OperandX64 dst, OperandX64 src1, OperandX64 src2, RoundingModeX64 roundingMode); // inexact
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void vsqrtpd(OperandX64 dst, OperandX64 src);
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void vsqrtps(OperandX64 dst, OperandX64 src);
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void vsqrtsd(OperandX64 dst, OperandX64 src1, OperandX64 src2);
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void vsqrtss(OperandX64 dst, OperandX64 src1, OperandX64 src2);
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void vmovsd(OperandX64 dst, OperandX64 src);
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void vmovsd(OperandX64 dst, OperandX64 src1, OperandX64 src2);
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void vmovss(OperandX64 dst, OperandX64 src);
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void vmovss(OperandX64 dst, OperandX64 src1, OperandX64 src2);
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void vmovapd(OperandX64 dst, OperandX64 src);
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void vmovaps(OperandX64 dst, OperandX64 src);
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void vmovupd(OperandX64 dst, OperandX64 src);
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void vmovups(OperandX64 dst, OperandX64 src);
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// Run final checks
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void finalize();
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// Places a label at current location and returns it
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Label setLabel();
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// Assigns label position to the current location
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void setLabel(Label& label);
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// Constant allocation (uses rip-relative addressing)
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OperandX64 i64(int64_t value);
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OperandX64 f32(float value);
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OperandX64 f64(double value);
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OperandX64 f32x4(float x, float y, float z, float w);
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OperandX64 bytes(const void* ptr, size_t size, size_t align = 8);
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2022-10-13 23:59:53 +01:00
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void logAppend(const char* fmt, ...) LUAU_PRINTF_ATTR(2, 3);
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2022-05-26 21:33:48 +01:00
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// Resulting data and code that need to be copied over one after the other
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// The *end* of 'data' has to be aligned to 16 bytes, this will also align 'code'
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std::vector<uint8_t> data;
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std::vector<uint8_t> code;
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std::string text;
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2022-10-13 23:59:53 +01:00
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const bool logText = false;
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2022-05-26 21:33:48 +01:00
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private:
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// Instruction archetypes
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void placeBinary(const char* name, OperandX64 lhs, OperandX64 rhs, uint8_t codeimm8, uint8_t codeimm, uint8_t codeimmImm8, uint8_t code8rev,
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uint8_t coderev, uint8_t code8, uint8_t code, uint8_t opreg);
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void placeBinaryRegMemAndImm(OperandX64 lhs, OperandX64 rhs, uint8_t code8, uint8_t code, uint8_t codeImm8, uint8_t opreg);
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void placeBinaryRegAndRegMem(OperandX64 lhs, OperandX64 rhs, uint8_t code8, uint8_t code);
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void placeBinaryRegMemAndReg(OperandX64 lhs, OperandX64 rhs, uint8_t code8, uint8_t code);
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void placeUnaryModRegMem(const char* name, OperandX64 op, uint8_t code8, uint8_t code, uint8_t opreg);
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void placeShift(const char* name, OperandX64 lhs, OperandX64 rhs, uint8_t opreg);
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void placeJcc(const char* name, Label& label, uint8_t cc);
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void placeAvx(const char* name, OperandX64 dst, OperandX64 src, uint8_t code, bool setW, uint8_t mode, uint8_t prefix);
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void placeAvx(const char* name, OperandX64 dst, OperandX64 src, uint8_t code, uint8_t coderev, bool setW, uint8_t mode, uint8_t prefix);
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void placeAvx(const char* name, OperandX64 dst, OperandX64 src1, OperandX64 src2, uint8_t code, bool setW, uint8_t mode, uint8_t prefix);
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2022-08-11 21:42:54 +01:00
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void placeAvx(
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const char* name, OperandX64 dst, OperandX64 src1, OperandX64 src2, uint8_t imm8, uint8_t code, bool setW, uint8_t mode, uint8_t prefix);
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// Instruction components
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void placeRegAndModRegMem(OperandX64 lhs, OperandX64 rhs);
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void placeModRegMem(OperandX64 rhs, uint8_t regop);
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void placeRex(RegisterX64 op);
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void placeRex(OperandX64 op);
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2022-10-07 00:55:58 +01:00
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void placeRexNoW(OperandX64 op);
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void placeRex(RegisterX64 lhs, OperandX64 rhs);
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void placeVex(OperandX64 dst, OperandX64 src1, OperandX64 src2, bool setW, uint8_t mode, uint8_t prefix);
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void placeImm8Or32(int32_t imm);
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void placeImm8(int32_t imm);
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void placeImm32(int32_t imm);
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void placeImm64(int64_t imm);
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void placeLabel(Label& label);
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void place(uint8_t byte);
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void commit();
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LUAU_NOINLINE void extend();
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uint32_t getCodeSize();
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// Data
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size_t allocateData(size_t size, size_t align);
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// Logging of assembly in text form (Intel asm with VS disassembly formatting)
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LUAU_NOINLINE void log(const char* opcode);
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LUAU_NOINLINE void log(const char* opcode, OperandX64 op);
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LUAU_NOINLINE void log(const char* opcode, OperandX64 op1, OperandX64 op2);
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LUAU_NOINLINE void log(const char* opcode, OperandX64 op1, OperandX64 op2, OperandX64 op3);
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LUAU_NOINLINE void log(const char* opcode, OperandX64 op1, OperandX64 op2, OperandX64 op3, OperandX64 op4);
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2022-05-26 21:33:48 +01:00
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LUAU_NOINLINE void log(Label label);
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LUAU_NOINLINE void log(const char* opcode, Label label);
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void log(OperandX64 op);
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const char* getSizeName(SizeX64 size);
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const char* getRegisterName(RegisterX64 reg);
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uint32_t nextLabel = 1;
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std::vector<Label> pendingLabels;
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std::vector<uint32_t> labelLocations;
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bool finalized = false;
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size_t dataPos = 0;
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uint8_t* codePos = nullptr;
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uint8_t* codeEnd = nullptr;
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};
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} // namespace CodeGen
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} // namespace Luau
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